MCHBAR Registers
R
5.1.10
C0DRC0—Channel A DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
120h
00000000h
R/W
Size:
32 bits
Access &
Default
Bit
Description
31:30
29
Reserved
R/W
0b
Initialization Complete (IC): This bit is used for communication of software state
between the memory controller and the BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete.
28:11
10:8
Reserved
R/W
Refresh Mode Select (RMS): This field determines whether refresh is enabled
000b
and, if so, at what rate refreshes will be executed.
000 = Refresh disabled
001 = Refresh enabled. Refresh interval 15.6 µsec
010 = Refresh enabled. Refresh interval 7.8 µsec
011 = Refresh enabled. Refresh interval 3.9 µsec
100 = Refresh enabled. Refresh interval 1.95 µsec
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other = Reserved
7
RO
0b
Reserved
104
Datasheet
INTEL [ INTEL ]
