EPBAR Registers—Egress Port Register Summary
R
6 EPBAR Registers—Egress Port
Register Summary
These registers are offset from the EPBAR base address.
Table 6-1. Egress Port Register Address Map
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
044h–047h
050h–053h
EPESD
EPLE1D
EPLE1A
EP Element Self Description
EP Link Entry 1 Description
EP Link Entry 1 Address
0000h
0100h
R/WO, RO
R/WO, RO
R/WO, RO
058h–
05Fh
000000000
0000000h
060h–063h
EPLE2D
EPLE2A
EP Link Entry 2 Description
EP Link Entry 2 Address
02000002h
R/WO, RO
RO
068h–
06Fh
000000000
0008000h
6.1
EP RCRB Configuration Register Details
Figure 6-1. Link Declaration Topology
(G)MCH
X16
PEG
(Port #2)
Link #2
(Type 1)
Link #1
(Type 0)
Egress Port
(Port #0)
Main Memory
Subsystem
Link #2
(Type 0)
Link #1
(Type 0)
DMI
(Port #1)
Link #1
(Type 0)
X4
Intel® ICH6
Egress Port
(Port #0)
Egress_LinkDeclar_Topo
Datasheet
109
INTEL [ INTEL ]
