MCHBAR Registers
R
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
10Eh
0000h
R/W
Size:
16 bits
This register is used to program the bank architecture for each Rank.
Bit
Access &
Default
Description
15:8
7:6
Reserved
R/W
00b
Rank 3 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
Rank 2 Bank Architecture
00 = 4 Bank.
5:4
3:2
1:0
R/W
00b
01 = 8 Bank.
1X = Reserved
Rank 1 Bank Architecture
00 = 4 Bank.
R/W
00b
01 = 8 Bank.
1X = Reserved
Rank 0 Bank Architecture
00 = 4 Bank.
R/W
00b
01 = 8 Bank.
1X = Reserved
Datasheet
101
INTEL [ INTEL ]
