82551IT — Networking Silicon
Table 17. Power Management Capability Register
Bits
20
Default
Read/Write
Description
0b (PCI)
Read Only
Reserved PCI.
PME# Clock. The 82551IT does not require a clock to generate a
power management event.
19
0b
Read Only
Read Only
Version. A value of 010b indicates that the 82551IT complies with of
the PCI Power Management Specification, Revision 2.2.
18:16
010b
7.1.20
Power Management Control/Status Register (PMCSR)
The Power Management Control/Status is a word register. It is used to determine and change the
current power state of the 82551IT and control the power management interrupts in a standard
manner.
Table 18. Power Management Control and Status Register
Bits
Default
Read/Write
Description
PME# Status. This bit is set upon a wake-up event. It is independent
of the state of the PME# Enable bit. If 1b is written to this bit, the bit will
be cleared. It also de-asserts the PME# signal and clears the PME#
status bit in the Power Management Driver Register. When the PME#
signal is enabled, the PME# signal reflects the state of the PME status
bit.
15
0b
Read/Clear
Data Scale. This field indicates the data register scaling factor. It
equals 1b for registers zero through eight and 0b for registers 9
through 15.
14:13
12:9
0b
0b
Read Only
Read Only
Data Select. This field is used to select which data is reported through
the Data register and Data Scale field.
8
0b
0b
Read Clear
Read Only
PME Enable. This bit enables the 82551IT to assert PME#.
Reserved. These bits are reserved and should be set to 0b.
7:5
Dynamic Data. The 82551IT does not support the ability to monitor
the power consumption dynamically.
4
0b
0b
Read Only
Read Only
3:2
Reserved. These bits are reserved and should be set to 0b.
Power State. This 2-bit field is used to determine the current power
state of the 82551IT and to set the 82551IT into a new power state.
The definition of the field values is as follows.
00 - D0
01 - D1
10 - D2
11 - D3
1:0
0b
Read/Write
50
Datasheet
INTEL [ INTEL ]
