82551IT — Networking Silicon
MDI Control Register: The MDI Control register allows the CPU to read and write information
from the PHY unit (or an external PHY component) through the Management Data Interface.
Receive DMA Byte Count: The Receive DMA Byte Count register keeps track of how many
bytes of receive data have been passed into host memory via DMA.
Flow Control Register: This register holds the flow control threshold value and indicates the flow
control commands to the 82551IT.
PMDR: The Power Management Driver Register provides an indication in memory and I/O space
that a wake-up interrupt has occurred.
General Control: The General Control register allows the 82551IT to enter the deep power-down
state and provides the ability to disable the Clockrun functionality.
General Status: The General Status register describes the status of the 82551IT’s duplex mode,
speed, and link.
Function Present State: The Function Present State register reflects the current state of each
condition that may cause a status change or interrupt.
Force Event: The Force Event register simulates the status change events for troubleshooting
purposes.
8.1.1
System Control Block Status Word
The System Control Block (SCB) Status Word contains status information relating to the
82551IT’s Command and Receive units.
Table 20. System Control Block Status Word
Bits
Name
Description
Command Unit (CU) Executed. The CX bit indicates that the CU has
completed executing a command with its interrupt bit set.
15
14
13
CX
Frame Received. The FR bit indicates that the Receive Unit (RU) has
finished receiving a frame.
FR
CU Not Active. The CNA bit is set when the CU is no longer active and in
either an idle or suspended state.
CNA
Receive Not Ready. The RNR bit is set when the RU is not in the ready
state. This may be caused by an RU Abort command, a no resources
situation, or set suspend bit due to a filled Receive Frame Descriptor.
12
RNR
Management Data Interrupt. The MDI bit is set when a Management Data
Interface read or write cycle has completed. The management data interrupt
is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
11
10
MDI
SWI
Software Interrupt. The SWI bit is set when software generates an
interrupt.
9
8
Reserved
FCP
This bit is reserved and should be set to 0b.
Flow Control Pause. The FCP bit is used as the flow control pause bit.
54
Datasheet
INTEL [ INTEL ]
