Networking Silicon — 82551IT
8.0
Control/Status Registers
8.1
LAN (Ethernet) Control/Status Registers
The 82551IT’s Control/Status Register (CSR) is shown in the figure Figure 19.
Figure 19. Control/Status Register
D31
Upper Word
SCB Command Word
D16
D15
Lower Word
D0
Offset
SCB Status Word
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
System Control Block General Pointer
PORT
EEPROM Control Register
Flash Control Register
Management Data Interface (MDI) Control Register
Receive Direct Memory Access Byte Count
Flow Control Register
PMDR
Reserved
General Control
Reserved
General Status
Reserved
Command Block Pointer
Reserved
Reserved
Function Event Register
Function Event Mask Register
Function Present State Register
Force Event Register
NOTE: In Figure 19 above, SCB is defined as the System Control Block of the 82551IT, and PMDR is defined
as the Power Management Driver Register.
SCB Status Word: The 82551IT places the status of its Command and Receive units and interrupt
indications in this register for the CPU to read.
SCB Command Word: The CPU places commands for the Command and Receive units in this
register. Interrupts are also acknowledged in this register.
SCB General Pointer: The SCB General Pointer register points to various data structures in main
memory depending on the current SCB Command word.
PORT Interface: The PORT interface allows the CPU to reset the 82551IT, force the 82551IT to
dump information to main memory, or perform an internal self test.
Flash Control Register: The Flash Control register allows the CPU to enable writes to an external
Flash.
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
an external EEPROM.
Datasheet
53
INTEL [ INTEL ]
