Networking Silicon — 82551IT
7.1.9.1
7.1.9.2
CSR Memory Mapped Base Address Register
The 82551IT requires one BAR for memory mapping. Software determines which BAR, memory
or I/O, is used to access the 82551IT CSR registers.
The memory space for the 82551IT CSR Memory Mapped BAR is 4 KB. The space is marked as
not prefetchable and is mapped anywhere in the 32-bit memory address space.
CSR I/O Mapped Base Address Register
The 82551IT requires one BAR for I/O mapping. Software determines which BAR, I/O or
memory, is used to access the 82551IT CSR registers. The I/O space for the 82551IT CSR I/O
BAR is 64 bytes.
7.1.9.3
7.1.9.4
Flash Memory Mapped Base Address Register
The Flash Memory BAR is a Dword register. The 82551IT physically supports a 128 KB Flash
device.
Expansion ROM Base Address Register
The Expansion ROM has a memory space of 1 MB and its BAR is a Dword register that supports a
128 KB memory via the 82551IT local bus. The Expansion ROM BAR can be disabled by setting
the Boot Disable bit located in the EEPROM (word Ah, bit 11). If the Boot Disable bit is set, the
82551IT returns a 0b for all bits in this address register, avoiding request of memory allocation for
this space.
7.1.10
Base Address Registry Summary
The preceding description of the Base Address Registers’ functions are listed in Table 15.
Table 15. Base Address Register Functions
Register Name
PCI Function
PCI Window
BAR0
BAR1
Memory CSR
I/O CSR
4 KB
4 KB
BAR2
Flash
128 KB
1 MB
Expansion BAR
BootROM
7.1.11
PCI Subsystem Vendor ID and Subsystem ID Registers
The Subsystem Vendor ID field identifies the vendor of an 82551IT based solution. The Subsystem
Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special
Interest Group (SIG).
The Subsystem ID field identifies the 82551IT based specific solution implemented by the vendor
indicated in the Subsystem Vendor ID field.
Datasheet
47
INTEL [ INTEL ]
