Networking Silicon — 82551IT
7.1.15
Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not
applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI
bus ownership when it initiates a transaction. The default value of this register for the 82551IT is
08h.
7.1.16
7.1.17
Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is
not applicable to non-master devices. This register defines how often a device needs to access the
PCI bus. The default value of this register for the 82551IT is 18h.
Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the
register defined for PCI Power Management. PCI Power Management has been assigned the value
of 01h. The 82551IT is fully compliant with the PCI Power Management Specification, Revision
2.2.
7.1.18
7.1.19
Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82551IT’s
capability list. Since power management is the last item in the list, this register is set to 0b.
Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the capabilities of the 82551IT related to power management. The 82551IT reports a value of
FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the
82551IT supports wake-up in the D3 state if power is supplied, either V or V
.
cc
AUX
Table 17. Power Management Capability Register
Bits
Default
Read/Write
Description
00011b
(no VAUX
PME# Support. This five-bit field indicates the power states in which
the 82551IT may assert PME#. The 82551IT supports wake-up in all
power states if it is fed by an auxiliary power supply (VAUX) and D0,
D1, D2, and D3hot if it is fed by PCI power.
)
31:27
Read Only
11111b
(VAUX
1b
)
D2 Support. If this bit is set, the 82551IT supports the D2 power
state.
26
25
Read Only
Read Only
D1 Support. If this bit is set, the 82551IT supports the D1 power
state.
1b
0b
Auxiliary Current. This field reports whether the 82551IT
implements the Data registers. The auxiliary power consumption is
the same as the current consumption reported in the D3 state in the
Data register.
24:22
21
Read Only
Read Only
Device Specific Initialization (DSI). The DSI bit indicates whether
special initialization of this function is required (beyond the standard
PCI configuration header) before the generic class device driver is
able to use it. DSI is required for the 82551IT after D3-to-D0 reset.
1b
Datasheet
49
INTEL [ INTEL ]
