80960JD
A
Table 16. Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) (pg. 26)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is
LO
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-
nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
20
MHz
ns
TC
CLKIN Period
50
125
TCS
TCH
CLKIN Period Stability
CLKIN High Time
±250
ps
(1, 2)
20
20
ns
Measured at
1.5 V (1)
TCL
TCR
TCF
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
ns
ns
ns
Measured at
1.5 V (1)
7
7
0.8 V to 2.0
V (1)
2.0 V to 0.8
V (1)
SYNCHRONOUS OUTPUT TIMINGS
TOV1
Output Valid Delay, Except ALE/ALE
Inactive and DT/R
3.5
18
ns
(3)
28
PRELIMINARY
INTEL [ INTEL ]
