80960JD
A
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 3 of 3)
Symbol
TBSOV2
TBSOF2
TBSIS2
Parameter
Min
3
Max
30
Units
ns
Notes
(1, 10)
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
3
30
ns
(1, 10)
Input Setup to TCK — All Inputs (Non-
Test)
4
ns
TBSIH2
Input Hold from TCK — All Inputs (Non-
Test)
6
ns
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is
LO
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-
nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
30
PRELIMINARY
INTEL [ INTEL ]
