80960JD
A
Pay special attention to the Test Reset (TRST) pin. It
is essential that the JTAG Boundary Scan Test
Access Port (TAP) controller initializes to a known
state whether it will be used or not. If the JTAG
Boundary Scan function will be used, connect a
pulldown resistor between the TRST pin and VSS. If
the JTAG Boundary Scan function will not be used
(even for board-level testing), connect the TRST pin
to VSS. Also, do not connect the TDI, TDO, and TCK
pins if the TAP Controller will not be used.
4.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS
pins separately feed the device’s functional units.
Power and ground connections must be made to all
80960JD power and ground pins. On the circuit
board, every VCC pin should connect to a power
plane and every VSS pin should connect to a ground
plane. Place liberal decoupling capacitance near the
80960JD, since the processor can cause transient
power surges.
Pins identified as NC must not be connected in
the system.
4.4
DC Specifications
Table 13. 80960JD DC Characteristics
Symbol
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Min
-0.3
2.0
Typ
Max
0.8
Units
Notes
VIL
V
V
V
V
VIH
VOL
VOH
VCC + 0.3
0.45
IOL = 5 mA
IOH = -1 mA
2.4
VCC - 0.5
IOH = -200 mA
VOLP
CIN
Output Ground Bounce
< 0.8
V
(1,2)
Input Capacitance
PGA
PQFP
f
f
= fMIN (2)
= fMIN (2)
CLKIN
CLKIN
12
10
pF
COUT
I/O or Output Capacitance
PGA
PQFP
12
10
pF
pF
CCLK
CLKIN Capacitance
PGA
PQFP
12
10
f
= fMIN (2)
CLKIN
NOTES:
1. Typical is measured with VCC = 5.0V and temperature = 25 °C.
2. Not tested.
24
PRELIMINARY
INTEL [ INTEL ]
