Electrical Specifications
Figure 2-4. V Static and Transient Tolerance
CC
Icc [A]
45 50
0
5
10
15
20
25
30
35
40
55
60
65
70
75
80
85
90
95
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VCC
Maximum
VCC
Typical
VCC
Minimum
NOTES:
1. The VCC_MIN and VCC_MAX load lines represent static and transient limits.
2. Refer to Table 2-9 for processor VID information for VCC
.
3. The load lines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCCSENSE and
V
SSSENSE pins.
2.10.2
VCC and VCACHE Overshoot Specification
The processor can tolerate short transient overshoot events where V exceeds the VID voltage or
CC
where V
exceeds the CVID voltage when transitioning from a high-to-low current load
CACHE
condition. This overshoot cannot exceed VID + V
or CVID + V
. (V
is the
OS_MAX,
OS_MAX
OS_MAX
maximum allowable overshoot above VID or CVID). These specifications apply to the processor
die voltage as measured across the V
and V
pins for Vcc, and V
CCSENSE
SSSENSE CC_CACHE_SENSE
and V
pins for CVID.
SS_CACHE_SENSE
Table 2-11. V and V
Overshoot Specification
CC
CACHE
Symbol
Parameter
Min
Max
Units
Figure
Notes
Magnitude of VCC overshoot
above VID or VCACHE
VOS_MAX
0.025
V
2-5
overshoot above CVID
Time duration of VCC
overshoot above VID or
TOS_MAX
5
µs
2-5
V
CACHE overshoot above CVID
32
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
