Electrical Specifications
Table 2-17. GTL+ and AGTL+ Asynchronous Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
VIL
VIH
VOH
IOL
ILI
Input Low Voltage
Input High Voltage
0
GTLREF - (10% * VTT
)
V
V
2
3,4,6
1,4,6
7
GTLREF + (10% * VTT
)
VTT
VTT
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
V
50
mA
µA
µA
Ω
N/A
8
± 200
± 200
12
8
ILO
Ron
9
5
NOTES:
1. All outputs are open-drain.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
4. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal
quality specifications in Section 3.
5. Refer to the Processor Signal Integrity Models for I/V characteristics.
6. The VTT referred to in these specifications refers to instantaneous VTT
.
7. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
8. Leakage to VSS with pin held at VTT
9. Leakage to VTT with pin held at 300 mV.
Table 2-18. SMBus Signal Group DC Specifications
Symbol
VIL
Parameter
Min
Max
Unit
Notes 1,2
Input Low Voltage
Input High Voltage
-0.30
0.30 * SM_VCC
3.465
V
V
VIH
VOL
IOL
0.70 * SM_VCC
Output Low Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
SMBus Pin Capacitance
0
0.400
V
N/A
N/A
N/A
3.0
mA
µA
µA
pF
ILI
± 10
ILO
± 10
CSMB
15.0
3
NOTES:
1. These parameters are based on design characterization and are not tested.
2. All DC specifications for the SMBus signal group are measured at the processor pins.
3. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
36
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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