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80502500E256 参数 Datasheet PDF下载

80502500E256图片预览
型号: 80502500E256
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 500MHz, CMOS, CPGA370, PGA-370]
分类和应用: 时钟外围集成电路
文件页数/大小: 76 页 / 564 K
品牌: INTEL [ INTEL ]
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Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz  
Figure 2. AGTL+ Bus Topology in a Uniprocessor Configuration  
Processor  
Chipset  
Figure 3. AGTL+ Bus Topology in a Dual-Processor Configuration  
Processor  
Chipset  
Processor  
2.2  
Clock Control and Low Power States  
Processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power  
consumption by stopping the clock to internal sections of the processor, depending on each  
particular state. See Figure 4 for a visual representation of the processor low power states.  
Figure 4. Stop Clock State Machine  
HALT Instruction and  
HALT Bus Cycle Generated  
1. Normal State  
2. Auto HALT Power Down State  
BCLK running.  
INIT#, BINIT#, INTR,  
SMI#, RESET#  
Normal execution.  
Snoops and interrupts allowed.  
STPCLK# Asserted  
STPCLK# De-asserted  
and Stop-Grant State  
STPCLK#  
Asserted  
STPCLK#  
De-asserted  
Snoop  
Event  
Occurs  
Snoop  
Event  
Serviced  
entered from  
AutoHALT  
Snoop Event Occurs  
Snoop Event Serviced  
3. Stop Grant State  
4. HALT/Grant Snoop State  
BCLK running.  
BCLK running.  
Snoops and interrupts allowed.  
Service snoops to caches.  
SLP#  
SLP#  
Asserted  
De-asserted  
5. Sleep State  
BCLK running.  
No snoops or interrupts allowed.  
BCLK  
BCLK  
Input  
Input  
Stopped  
Restarted  
6. Deep Sleep State  
BCLK stopped.  
No snoops or interrupts allowed.  
PCB757a  
12  
Datasheet