Signal Description
2.18.2.2
RSTIN# Mechanism
Once the system is up and running, a full system reset may be required to recover from system
error conditions related to various device or subsystem failures. This hot reset mechanism is
provided to accomplish this recovery without clearing the ‘sticky’ error status bits useful to track
the cause of the device or subsystem error conditions.
A hot reset can be initiated by asserting the RSTIN# signal. This signal is treated as an
asynchronous input to the Intel® 6702PXH 64-bit PCI Hub, meaning that there is no assumed
relationship between the assertion or the de-assertion of RSTIN# and the host reference clock.
2.18.2.3
2.18.2.4
PCI Express Reset Mechanism
There is no reset signal on the PCI Express bus, as all reset communication is in-band. The north
PCI Express device (such as an MCH) communicates the fact that it is entering and coming out of
a reset using messages. The Intel® 6702PXH 64-bit PCI Hub will respond by also going through a
reset. This incoming message by nature of the PCI Express protocol is asynchronous to the
reference clock. However, when the Intel® 6702PXH 64-bit PCI Hub goes through a reset for its
own reasons (PWROK, RSTIN#) the link goes down, which will be inferred by the north device
and handled with a hot plug reset (if hot plug is enabled).
Software PCI Reset (or SBR - Secondary Bus Reset)
Commonly referred to as the Secondary Bus Reset (SBR), this reset is initiated by a write to the
bridge control register and resets only the particular PCI segment, thus this reset is not applicable to
the Intel® 6702PXH 64-bit PCI Hub. This reset can be used for various reasons in including
recovering from error conditions on the secondary bus, redoing enumeration, changing the
operating frequency of the bus (33/66/100/133 MHz), changing the operating mode of the bus (PCI
or PCI-X), etc. This reset is synchronous to the PCI clock domain in which it is used. SBR is
strictly restricted to the particular PCI segment and affects neither the other PCI segment nor the
rest of the Intel® 6702PXH 64-bit PCI Hub logic. Writes to the bridge control register with a new
frequency etc., will have no effect until the SBR happens. The power up frequency of the PCI bus
is shown in Table 2-37. When hot plug is enabled the bus always powers up in PCI 33 MHz mode.
With hot plug disabled the frequency depends on the PAM66EN, PA133EN, PAPCIXCAP and
HPA_SOC pins.
Table 2-37. Power-On Frequency of Intel® 6702PXH 64-bit PCI Hub
PCIXCAP
(on the card)
PCI Capability
PCI-X Capability
M66EN
133EN
33 MHz
66 MHz
Not Capable
Not Capable
GND
X
X
GND
GND
1k-10kΩ pull-
up
33 MHz
66 MHz
33 MHz
66 MHz
33 MHz
66 MHz
PCI-X 66 MHz
PCI-X 66 MHz
PCI-X 100 MHz
PCI-X 100 MHz
PCI-X 133 MHz
PCI-X 133 MHz
GND
No Connect
GND
X
Pull-down 10 kΩ 5%
Pull-down 10 kΩ 5%
X
Pull-down
Pull-down
Pull-up
Pull-up
0.01 µF capacitor to GND
0.01 µF capacitor to GND
0.01 µF capacitor to GND
0.01 µF capacitor to GND
No Connect
GND
No Connect
70
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
