Signal Description
• Live Data: The value of the pins (address, data, byte enables, header) that caused the error.
The rules are:
• Cycle Errors: Target Abort and Master Abort are cycle errors. In these types of errors, the
context data is stored along with the error indication. This is stored as opposed to live data
because there is nothing fundamentally wrong with the live data – it is the context data that
resulted in the error.
• Address Parity Errors: Live data is stored in these types of errors, because the
Intel® 6702PXH 64-bit PCI Hub does not have enough information as to what the intended
address was supposed to be, and the live data is needed to decode the parity error.
• Data Parity Errors: Live data is stored for the erroneous data, and context address is stored
for the address. The live data is needed to decode the parity error, and the context address is
needed in case software can recover.
The Intel® 6702PXH 64-bit PCI Hub only logs errors for cycles where it will do work. For
example, if a PCI cycle had an address parity error, and the Intel® 6702PXH 64-bit PCI Hub does
not assert PADEVSEL# for that cycle, then that would not be logged as an error. Also, error
transaction logging on the PCI bus is decoupled from the error transaction logging on the PCI
Express bus and this is possible because transaction error logging for a transaction that transits the
Intel® 6702PXH 64-bit PCI Hub, happens only once at the originating interface.
2.20.2.3
2.20.3
2.20.4
Error Escalation
To support error reporting on the PCI bus, the Intel® 6702PXH 64-bit PCI Hub implements
PAPERR# and PASERR# signals. Also to escalate the PCI errors on to PCI Express, the
Intel® 6702PXH 64-bit PCI Hub supports the ERR_COR, ERR_UNC, ERR_FATAL messages on
the PCI Express bus.
SHPC Errors
Refer to the Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0 for details of
SHPC error logging and reporting implemented by the Intel® 6702PXH 64-bit PCI Hub. In
addition, the Intel® 6702PXH 64-bit PCI Hub provides for a way to route all SHPC interrupts to
platform firmware instead of to the OS, via a vendor-specific message on the PCI Express bus.
Core Errors
Core errors in the Intel® 6702PXH 64-bit PCI Hub are SRAM soft errors. Data errors because of
SRAM errors are forwarded with poisoned data to the appropriate end point. If the end-point is an
internal device, then the data is dropped and an error message/completion (if required) signaled. If
the end point is on either the PCI or PCI Express buses, the data is forwarded to the bus with the
data poisoned. This allows for the PCI/PCI Express bus endpoints to determine the severity of the
error and deal with it appropriately. SRAM soft errors resulting in address parity errors are far more
severe. These transactions will be dropped and error message/completion generated.
Core errors will be logged with a single bit in the RAS_STS register for status. There will be a
RAS_IQE register to capture individual SRAM errors from various units.
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Intel® 6702PXH 64-bit PCI Hub Datasheet
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