Signal Description
These clocks are fed into internal logic contained within the Intel® 6702PXH 64-bit PCI Hub to
generate a 2.5 GHz clock that runs the PCI Express interface and the Intel® 6702PXH 64-bit PCI
Hub core. This 2.5 GHz clock is then fed into additional internal logic that converts the clock
frequency to one of the PCI/PCI-X supported frequencies (33/66/100/133 MHz for PCI or PCI-X
Mode 1).
Intel® 6702PXH 64-bit PCI Hub PCI Bus segment supports 7 PCI output clocks, called
PAPCLKO[6:0]. The PAPCLKO[6] output clock is connected to the PCI feedback clock input
PAPCLKI.
2.18.2
Component Reset
There are five types of reset that can be performed on the Intel® 6702PXH 64-bit PCI Hub. These
are listed from highest level of reset to the lowest level reset:
• PWROK – this signal indicates stable power when high and causes an asynchronous reset of
the entire Intel® 6702PXH 64-bit PCI Hub chip when low.
• RSTIN# – this is also an asynchronous reset to the Intel® 6702PXH 64-bit PCI Hub and can
be used for resetting the Intel® 6702PXH 64-bit PCI Hub for the front panel reset.
• PCI Express Reset – this is message coming on the PCI Express interface and is not a
physical signal.
• Software PCI Reset – this reset is initiated by writing to bridge control register of the PCI
configuration space. This reset is specific to the particular bridge that the software wishes to
reset. This is also commonly referred to as the SBR (secondary bus reset).
• Hot plug Reset – This reset is caused by the act of writing to the command register with a
frequency change command.
2.18.2.1
PWROK Mechanism
All the voltage sources in the system are tracked by a system component that asserts the PWROK
signal only after all the voltages have been stable for some predetermined time. The
Intel® 6702PXH 64-bit PCI Hub receives the PWROK signal as an asynchronous input, meaning
that there is no assumed relationship between the assertion or the de-assertion of PWROK and the
reference clock. While the PWROK is de-asserted the Intel® 6702PXH 64-bit PCI Hub will hold
all logic in reset.
The PWROK reset will clear all internal state machines and logic, and initialize all registers to their
default states including ‘sticky’ error bits that are persistent through all other reset classes. To
eliminate potential system reliability problems, all devices are also required to either tristate their
outputs or to drive them to safe levels during such a power on reset.
The PWROK signal is used to indicate when the power supply is within its specified voltage
tolerance and is stable. It also initializes the Intel® 6702PXH 64-bit PCI Hub’s state machines and
other logic once power supplies stabilize. On power up, the assertion of PWROK is delayed 100ms
(TPVPERL) from the power rails achieving specified operating limits. Also, within this time, the
reference clocks (PCI Express clocks) become stable at least TPWROK-CLK (100 µS) before
PWROK is asserted. Refer to the PCI Express specification for details of the relationship between
PWROK assertion and the clocks and power being stable at the input of the Intel® 6702PXH
64-bit PCI Hub.
For the Intel® 6702PXH 64-bit PCI Hub in PCI-X Mode 1, PAPCIRST# is asserted for 2 ms after
PWROK goes high.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
