Signal Description
2.20
Error Handling
When integrity errors occur on the PCI or PCI Express buses, the Intel® 6702PXH 64-bit PCI Hub
implements the specified error logging and escalation actions as per the interface rules. For
example, errors encountered on the PCI interface follow the logging and escalation rules of the PCI
protocol. Beyond the set of escalation and error logging mandated by the interface specifications,
the Intel® 6702PXH 64-bit PCI Hub also implements some chipset-specific error logging and
escalation mechanisms to aid system software/driver in a more graceful error recovery and also for
system debug.
The error escalation mechanism implemented by the Intel® 6702PXH 64-bit PCI Hub can be fully
masked. This provides the platform software with the ability to pick and choose what it wants to do
on any of the error conditions. All Intel® 6702PXH 64-bit PCI Hub-specific logging registers are
sticky, that is, these registers retain their values through any chip reset other than a power cycle
reset.
2.20.1
PCI Express Errors
PCI Express errors are classified as either correctable errors or uncorrectable errors. Correctable
errors are those where hardware exists to correct the errors. Uncorrectable errors are errors where
hardware does not exist to correct the errors. Uncorrectable errors are further classified into fatal
and non-fatal errors, with non-fatal errors indicating an unreliable link. PCI Express supports three
different error messages to support these error classes – ERR_COR, ERR_UNC and ERR_FATAL.
Refer to the PCI Express Base Specification, Revision 1.0a for details of the various PCI Express
errors and how they are signaled and escalated.
PCI Express error logging specifies a set of advanced transaction logging registers as an added
capability.
2.20.2
PCI Errors
PCI and PCI-X protocol errors include several sources of error, such as address and data parity
errors, split completion errors, master aborts and target aborts. Some of these are fatal and some are
non-fatal. The PCI-X specification specifies a set of rules on how a bridge must behave on a variety
of error conditions that could happen on the bus. The Intel® 6702PXH 64-bit PCI Hub implements
those rules on the PCI bus along with the Intel® 6702PXH 64-bit PCI Hub-specific error logging
and routing control to aid the system software/driver in error recovery and debug
2.20.2.1
Error Types
PCI errors are classified into two categories, those that are considered fatal and those that are
considered non-fatal. Fatal errors are those that have the potential to cause data corruption and
hence software must be careful to contain and escalate these errors (if needed). Non-fatal errors are
those errors that do not cause any data corruption, and include driver errors such as master aborts
on the PCI bus and target errors such as target abort. All errors on the PCI bus are uncorrectable
and will be forwarded to the PCI Express bus as such.
The non-fatal class of errors is:
• Target Aborts on the PCI bus
• Master Aborts on the PCI bus
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Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
