3.5.1.48 Offset 6Ch: EXP_CAPSTR – PCI Express* Power
Management Capability Structure Register (D0:F0, F2).....................107
3.5.1.49 Offset 70h: EXP_PMSTSCNTL – PCI Express* Power
Management Status and Control Register (D0:F0, F2).......................108
3.5.1.50 Offset 78h: SHPC_CAPID—SHPC Capability Identifier
Register (D0:F0, F2) ...........................................................................109
3.5.1.51 Offset 79h: SHPC_NXTP—SHPC Next Item Pointer Register
(D0:F0, F2)..........................................................................................109
3.5.1.52 Offset 7Ah: SHPC_DWSEL—SHPC DWORD Select Register
(D0:F0, F2)..........................................................................................109
3.5.1.53 Offset 7Bh: SHPC_STS—SHPC Status Register (D0:F0, F2)............110
3.5.1.54 Offset 7Ch: SHPC_DWORD—SHPC Data Register (D0:F0, F2).......110
3.5.1.55 Offset D8h: PX_CAPID—PCI-X Capability Identifier Register
(D0:F0, F2)..........................................................................................110
3.5.1.56 Offset D9h: PX_NXTCP—PCI-X Next Capabilities Pointer
Register (D0:F0, F2) ...........................................................................111
3.5.1.57 Offset DAh: PX_SSTS—PCI-X Secondary Status
Register (D0:F0, F2) ...........................................................................111
3.5.1.58 Offset DCh: PX_BSTS—PCI-X Bridge Status Register
(D0:F0, F2)..........................................................................................112
3.5.1.59 Offset ECh: PX_ECCFA – Bridge ECC Error First Address
Register (D0:F0, F2) ...........................................................................113
3.5.1.60 Offset F0h: PX_ECCSA – Bridge ECC Error Second
Address Register (D0:F0, F2) .............................................................113
3.5.1.61 Offset F4h: BG_ECCATTR — Bridge ECC Attribute
Register (D0:F0, F2) ...........................................................................113
PCI Express* to PCI Bridges (D0:F0, F2) Enhanced.......................................................114
3.6
3.6.1
Configuration Registers.....................................................................................114
3.6.1.1 Offset 100h: ENH_CAP – PCI Express* Enhanced
Capability Register (D0:F0, F2)...........................................................114
3.6.1.2 Offset 104h: ERRUNC_STS – PCI Express*
Uncorrectable Error Status Register (D0:F0, F2)................................114
3.6.1.3 Offset 108h: ERRUNC_MSK – PCI Express*
Uncorrectable Error Mask Register (D0:F0, F2) .................................115
3.6.1.4 Offset 10Ch: ERRUNC_SEV – PCI Express*
Uncorrectable Error Severity Register (D0:F0, F2).............................116
3.6.1.5 Offset 110h: ERRCOR_STS – PCI Express*
Correctable Error Status Register (D0:F0, F2)....................................117
3.6.1.6 Offset 114h: ERRCOR_MSK – PCI Express*
Correctable Error Mask Register (D0:F0, F2) .....................................117
3.6.1.7 Offset 118h: ADVERR_CNTL – Advanced Error
Capabilities and Control Register (D0:F0, F2) ....................................118
3.6.1.8 Offset 11Ch: EXP_TXNHDLOG – PCI Express*
Transaction Header Log Register (D0:F0, F2)....................................118
3.6.1.9 Offset 12Ch: UNC_PXERRSTS – Uncorrectable
PCI/PCI-X Error Status Register (D0:F0, F2)......................................119
3.6.1.10 Offset 130h: UNC_PXERRMSK – Uncorrectable
PCI/PCI-X Error Mask Register (D0:F0, F2) .......................................120
3.6.1.11 Offset 134h: UNC_PXERRSEV – Uncorrectable
PCI/PCI-X Error Severity Register (D0:F0, F2)...................................121
3.6.1.12 Offset 138h: UNC_PXERRPTR – Uncorrectable
PCI/PCI-X Error Pointer Register (D0:F0, F2) ....................................122
3.6.1.13 Offset 13Ch: PX_TXNHDLOG – PCI/PCI-X
Uncorrectable Transaction Header Log (D0:F0, F2)...........................122
302628-002
7
INTEL [ INTEL ]
