2.12
Hot Plug Controllers.......................................................................................................... 47
2.12.1 Mode Determination ........................................................................................... 47
2.12.2 Output Control .................................................................................................... 48
2.12.3 Input Control ....................................................................................................... 49
2.12.4 Serial Mode Operation........................................................................................ 49
2.12.4.1 Serial Input Stream............................................................................... 50
2.12.4.2 Serial Output Stream............................................................................ 50
2.12.5 Parallel Mode Operation..................................................................................... 51
2.12.6 One-Slot-No-Glue Mode..................................................................................... 52
2.12.6.1 Driving Bus To Ground When PCI Card is Disconnected .................... 52
2.12.6.2 Aborting Outbound PCI Cycles When Card is Disconnected............... 53
2.12.7 Initialization......................................................................................................... 54
2.12.7.1 In-box Architecture ............................................................................... 54
2.12.7.2 Remote-I/O-Box Architecture ............................................................... 54
2.12.8 M66EN Pin Handling .......................................................................................... 54
2.12.9 Hot Plug Interrupts.............................................................................................. 55
2.12.9.1 MSI and Pin Interrupts.......................................................................... 55
2.12.9.2 ACPI Support ....................................................................................... 55
2.12.10 Error Handling..................................................................................................... 55
2.12.11 Assumptions and Intel® 6700PXH 64-bit PCI Hub Requirements ..................... 56
2.12.11.1MRL Opening during the Sequence .................................................... 56
2.12.11.2Power Fault.......................................................................................... 56
Addressing ........................................................................................................................ 56
2.13.1 I/O Window Addressing ...................................................................................... 56
2.13.1.1 Mode I/O Access.................................................................................. 56
2.13.2 Memory Window Addressing.............................................................................. 57
2.13.2.1 Mode Memory Access.......................................................................... 57
2.13.2.1.18Memory Accesses to I/OxAPIC and SHPC Memory Space ............. 59
2.13.3 VGA Addressing ................................................................................................. 59
2.13.3.1 Mode Access Mechanism .................................................................... 59
Transaction Ordering ........................................................................................................ 59
2.14.1 Intel® 6700PXH 64-bit PCI Hub Transaction Ordering....................................... 59
2.14.1.1 Inbound Transaction Ordering.............................................................. 60
2.14.1.2 Outbound Transaction Ordering........................................................... 60
I/OxAPIC Interrupt Controller (Functions 1 and 3) ............................................................ 61
2.15.1 Interrupt Support................................................................................................. 61
2.15.1.1 PCI IRQ# Interrupts.............................................................................. 61
2.15.1.2 PCI Message Signaled Interrupts (MSI)............................................... 61
2.15.2 PCI Express* Legacy INTx Support and Boot Interrupt...................................... 61
2.15.3 Buffer Flushing.................................................................................................... 62
2.15.4 EOI Special Cycles............................................................................................. 62
2.15.5 Interrupt Delivery ................................................................................................ 62
SMBus Interface................................................................................................................ 63
2.16.1 SMBus Commands............................................................................................. 64
2.16.2 Initialization Sequence........................................................................................ 65
2.16.3 Configuration And Memory Reads...................................................................... 66
2.16.4 Configuration and Memory Writes ...................................................................... 67
2.16.5 Error Handling..................................................................................................... 69
2.16.6 SMBus Interface Reset....................................................................................... 70
2.16.7 Configuration Access Arbitration ........................................................................ 70
2.13
2.14
2.15
2.16
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