2.17
System Setup.....................................................................................................................70
2.17.1 Clocking...............................................................................................................70
2.17.2 Component Reset................................................................................................71
2.17.2.1 PWROK Mechanism .............................................................................72
2.17.2.2 RSTIN# Mechanism..............................................................................72
2.17.2.3 PCI Express* Reset Mechanism...........................................................72
2.17.2.4 Software PCI Reset (or SBR - Secondary Bus Reset)..........................73
2.17.2.5 Hot Plug Reset......................................................................................73
Reliability, Availability, and Serviceability (RAS)................................................................74
2.18.1 PCI Express* Error Handling...............................................................................74
2.18.2 PCI Error Protection ............................................................................................74
2.18.3 PCI Standard Hot Plug Controller........................................................................74
2.18.4 SMBus.................................................................................................................74
Error Handling....................................................................................................................74
2.19.1 PCI Express* Errors ............................................................................................75
2.19.2 PCI Errors............................................................................................................75
2.19.2.1 Error Types ...........................................................................................75
2.19.2.2 Error Logging ........................................................................................75
2.19.2.3 Error Escalation.....................................................................................77
2.19.3 SHPC Errors........................................................................................................77
2.19.4 Core Errors..........................................................................................................77
2.19.5 Global Error Register...........................................................................................77
2.18
2.19
3
Register Description.........................................................................................................79
3.1
3.2
3.3
3.4
3.5
PCI Configuration Registers ..............................................................................................79
Memory-Mapped Registers................................................................................................80
SMBus Port Registers........................................................................................................80
Register Nomenclature and Access Attributes ..................................................................80
PCI Express*-to-PCI Bridges (D0:F0, F2)..........................................................................81
3.5.1
Configuration Registers.......................................................................................81
3.5.1.1 Offset 00h: VID—Vendor ID Register (D0:F0, F2)................................84
3.5.1.2 Offset 02h: DID—Device ID Register (D0:F0, F2) ................................84
3.5.1.3 Offset 04h: PCICMD—PCI Command Register (D0:F0, F2) ................84
3.5.1.4 Offset 06h: STS—Status Register (D0:F0, F2).....................................86
3.5.1.5 Offset 08h: REVID—Revision ID Register (D0:F0, F2).........................87
3.5.1.6 Offset 09h: CC—Class Code Register (D0:F0, F2) ..............................87
3.5.1.7 Offset 0Ch: CLS—Cache Line Size Register (D0:F0, F2) ....................87
3.5.1.8 Offset 0Dh: MLT—Master Latency Timer Register (D0:F0, F2)............88
3.5.1.9 Offset 0Eh: HEADTYP—Header Type Register (D0:F0, F2)................88
3.5.1.10 Offset 10h: SHPC_BAR—SHPC 64-bit Base Address Register
(D0:F0, F2)............................................................................................88
3.5.1.11 Offset 18h: PBN—Primary Bus Number Register (D0:F0, F2) .............89
3.5.1.12 Offset 19h: SCBN—Secondary Bus Number Register
(D0:F0, F2)............................................................................................89
3.5.1.13 Offset 1Ah: SBBN—Subordinate Bus Number Register
(D0:F0, F2)............................................................................................89
3.5.1.14 Offset 1Bh: SLT—Secondary Latency Timer (D0:F0, F2).....................90
3.5.1.15 Offset 1Ch: IOB—I/O Base Register (D0:F0, F2) .................................90
3.5.1.16 Offset 1Dh: IOL—I/O Limit Register (D0:F0, F2) ..................................91
3.5.1.17 Offset 1Eh: SECSTS—Secondary Status Register
(D0:F0, F2)............................................................................................91
3.5.1.18 Offset 20h: MB—Memory Base Register (D0:F0, F2)...........................93
302628-002
5
INTEL [ INTEL ]
