Transparent Mode
10 Transparent Mode
Figure 10-1 shows the typical architecture of a DRAM with a 4 bit wide data path. The
memory array operates at 100 to 200 MHz. With a pre-fetch of 4, there are 4 bits of
data on each array access, allowing us to clock data in or out at 400 MHz. This 4 to 1
multiplexing and de-multiplexing is performed in the input register or output
multiplexer.
Figure 10-1. DRAM Architecture
10.1
Transparent Mode
Refer to the JEDEC publication: FB-DIMM Draft Specification: Design for Test, Design
for Validation (DFx) Specification for information regarding transparent mode.
Transparent mode is designed to allow access to the DRAM behind the AMB. In this
mode high speed pins are converted into low speed pins and mapped to DRAM pins.
The objective is to allow the use of existing test equipment and manufacturing
processes. The tester must be capable of operation at 200 MHz. Transparent mode
offers potential improvements in test capacity over traditional DIMMs. In this mode,
FBD requires only 60 active pins to test the DIMM.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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