Transparent Mode
Table 10-1. Additional Signals in Transparent Mode
Transparent
Mode Signal
Name
Pin Count
Frequency
Direction
Definition
TCKE[1:0]
TCS#[1:0]
TODT
2
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
In
In
In
In
In
In
In
In
In
In
In
In
Out
Controls CKE[1:0]{A,B}
2
1
Controls both ODT[1:0]{A,B}
Controls WE{A,B}
TRAS#
1
TCAS#
1
TWE#
1
TBA[2:0]
TA[14:0]
TDRV
3
15
1
Tester signal to drive data on writes
Tester signal to compare on reads
Early data to each byte
TCMP
1
TDQ[15:8]
TDQ[7:0]
8
8
Late data to each byte
TPF[8:0] or
TDQO[15:0]
9 or 16
Used for pass/fail (8:0) or direct access (15:0)
Sum of receivers
Sum of drivers
44
16
10.1.3
Transparent Mode to FBD Pin Mapping
The FBD pin mapping is shown in Table 10-2.
Table 10-2. Mapping of FBD Pins in Transparent Mode
Transparent Mode Signal
Name
FBD Pin Name
Count
Speed
Comment
SN[0], SN[0]
2
200 MHz
TCKE[1:0]
TCS#[1:0]
TODT
SN[1], SN[1]
SN[2],
2
1
1
1
1
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
SN[2]
TRAS#
SN[3],
TCAS#
SN[3]
TWE#
SN[4], SN[4]
SN[5]
TBA[2:0]
SN[13:6], SN[13:6]
PS[8]
16
1
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
TA[15:0]
TDRV
PS[8]
1
TCMP
PS[7:0]
8
TDQ[15:8]
TDQ[7:0]
TPF[8:0]
Early data
PS[7:0]
8
Late data
SS[8:0]
9
Pass/Fail mode
(TRANSCFG.ENDOUT =0)
PN[13:7],
SS[8:0]
16
200 MHz
TDQO[15:0]
Data output mode
(TRANSCFG.ENDOUT =1)
Total Pins
Intel® 6400/6402 Advanced Memory Buffer Datasheet
101
INTEL [ INTEL ]
