Reset
9.4.5
Timing Diagrams
Figure 9-1. Cold Power-Up Reset
AMB Cold Power-Up Reset Sequence
Inputs to AMB
1.8 V supply
1.5, 3.3 V supplies
Ref clk
Stable
At least 2 msec
RESET#
At least 200 usec
SMBus
FBD link
Quiet
Pgm phys link regs
Disabled
Link init and cal AMB config EI
Link init
Bring up DRAM ifc
Outputs from AMB
CKE
DRAM clk
Stable
Nxt Æ Cur updated
by this time
Inputs: value irrelevant.
Outputs: value unknown
Figure 9-2. AMB Fast Reset Sequence
AMB Fast Reset Sequence
(DISSREXIT not Set)
Inputs to AMB
Power supplies and
Ref clk stable
RESET# high
Nxt Æ Cur updated
by this time
TS1
TS2
TS3
TS2
L0
L0
EI
TS0
L0
Primary SB FBD
TS1
TS3
Secondary NB FBD
EI
TS0
L0
0's
Outputs from AMB
TS1
TS2
TS3
Secondary SB FBD
Primary NB FBD
L0
EI
TS0
L0
TS1
TS2
TS3
EI
TS0
L0
L0
0's
Precharge All
& AutoRefresh
on-going
SRF Entry
SRF Exit
SRF Exit
DRAM Commands
CKE
DRAM clks
Stable
May change
Stable
Internal Signals
Non-Sticky Reset
0001
96
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
