Reset
9.5
I/O Initialization
9.5.1
FBD Channel Initialization
Channel initialization states and uses of fast reset are described in the FB-DIMM
Architecture and Protocol Specification.
9.5.2
DDR
Analog compensation commences at power-up. It’s completed by “RESET#”
deassertion. After the FBD link reaches L0 state, setting the DRC.CKEN configuration
bit enables CKE.The DDR interface is now ready for calibration.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
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