Reset
• All internal register bits are set to their default values, including any error logging
bits that are normally not reset by the channel reset.
• The initialization FSM is put into the disable state. All internal state machines are
put in their default state.
• All southbound and northbound Tx outputs are put into electrical idle (EI) mode. All
Tx outputs stay in EI mode until the appropriate initialization state after
deassertion of RESET#.
9.1.3
Power-Up and Suspend-to-RAM Considerations
In a suspend to RAM environment the DRAMs are put into self-refresh mode, and the
FBD channel power may be removed. The DRAM power supply remains active. This
supply is used by the AMB DRAM interface I/O circuits. The AMB must keep the CKE
pins low, without glitches through this transition.
RESET# should be asserted before channel power goes away when entering S3.
DDR control and clock signals will be pulled low during initial power up. This may be
done with a voltage detection circuit. CKE must be maintained low during this time
without glitches to prevent the DRAMs from exiting self refresh mode. The RESET#
signal will remain low during the power-up sequence, for at least 1mS after power and
clocks are stable. The CKE signals must remain low until a command is received that
takes the CKE signals high. This could be an exit self refresh command, or any of the
DRAM CKE commands.
9.2
Reset Types
Types of reset:
• Hard resets occur when the RESET# signal is low. This usually occurs at power up.
• Fast resets occur when there is a reset event on the primary southbound FBD Link.
• SMBus resets affect only the SMBus interface.
9.3
Pads Controlling Reset
The AMB resets are controlled by the RESET# pad and the primary southbound FBD
link pads. The RESET# pad resets the chip at power up. When the primary southbound
FBD link pads indicate EI, a fast reset is started.
9.3.1
RESET# Pad
The low true RESET# pad is controlled by the platform which holds it low until after
power and SCK/SCK are stable. RESET# asynchronously resets most of the chip to a
safe initial state. The PLLs and TAP are not reset.When RESET# goes high, logic
running on REFCLK waits an appropriate amount of time and then resets the core. Logic
running on REFCLK is reset by RESET# directly. As the chip comes out of reset, the
Primary South FBD Link is expected to be in a reset state. As the link sequences
through the first initialization sequence after power up, the AMB will not generate any
DRAM commands other than to maintain CKE low and enable DRAM clocks at the
appropriate time.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
