10-2 Block Diagram for the AMB in transparent mode ..................................................100
10-1 Transparent Mode Timing .................................................................................103
10-2 Transparent Mode Write Timing .........................................................................104
10-3 Transparent Mode Read Timing..........................................................................105
10-4 BL=8 Read Timing ...........................................................................................105
11-1 Range and Full Address Spaces..........................................................................117
11-2 Fast Y Address Sequencing ...............................................................................119
11-3 Fast X Address Sequencing ...............................................................................120
11-4 Fast XY Address Sequencing Examples ...............................................................121
11-5 MemBIST Circular Shift and LFSR Data Block Diagram ..........................................124
11-6 MemBIST Block Diagram ..................................................................................138
11-7 MBFSM Diagram ..............................................................................................139
11-8 CS State Machine ............................................................................................141
12-1 Pinout Configuration.........................................................................................143
12-2 Bottom View ...................................................................................................152
12-3 Top View ........................................................................................................153
12-4 Package Stackup .............................................................................................154
Tables
3-1
DQS Association with DQ/CB Pins in x8 and x4 Mode..............................................27
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
4-1
(See Note 1).....................................................................................................37
AMB Operating DC Electrical Parameters...............................................................37
Power Values for x8 DIMMS ................................................................................38
Power Values for x4 DIMMs.................................................................................41
AMB FB-DIMM Timing/Electrical ...........................................................................44
AMB FB-DIMM Latency .......................................................................................44
Recommended Operating Conditions for DRAM Interface.........................................45
Advance Memory Buffer Component DDR2 Electrical Timing Specifications.................50
Advance Memory Buffer DDR2 Package Lengths.....................................................51
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10 Recommended Operating Conditions for SMBUS Interface .......................................51
4-11 Recommended Operating Conditions for RESET and BFUNC Pins...............................51
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
6-3
6-4
6-5
7-1
7-2
7-3
8-1
8-2
8-3
DDR Pins Shared With LAI Functionality................................................................56
List of Pins Required to Enable Debug With LAI Functionality ...................................56
LAI Mode Added Signals .....................................................................................56
List of Shared DDR/LAI Pins ................................................................................57
Typical FBD Southbound Command Frame ............................................................59
LAI Local Events................................................................................................62
LAI Event Selection............................................................................................63
Link Errors in Initialization ..................................................................................71
Link Errors in Normal Operation...........................................................................72
DDR Errors .......................................................................................................73
Host Protocol Errors ...........................................................................................73
Other Errors......................................................................................................74
SMBus Command Encoding.................................................................................78
SMBus Protocol Addressing Fields ........................................................................78
Status Field Encoding for SMBus Reads.................................................................79
PLL Clocks ........................................................................................................85
AMB Clock Ratios...............................................................................................86
Clock Pins.........................................................................................................86
10-1 Additional Signals in Transparent Mode...............................................................101
8
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
