Introduction
1.1.1
Transparent Mode for DRAM Test Support
In this mode, the AMB will provide lower speed tester access to DRAM pins through the
FBD I/O pins. This allows the tester to send an arbitrary test pattern to the DRAMs.
Transparent mode only supports a maximum DRAM frequency equivalent to DDR2 400.
Transparent mode functionality:
• Reconfigures FBD inputs from differential high speed link receivers to two single
ended lower speed receivers (~200 MHz)
• These inputs directly control DDR2 Command/Address and input data that is
replicated to all DRAMs
• Uses low speed direct drive FBD outputs to bypass high speed Parallel/Serial
circuitry and provide test results back to tester
1.1.2
Debug and Logic Analyzer Interface
When optional LAI functionality is supported, the AMB can be used to support the
connection of FBD links to a Logic Analyzer (LA) for debug.
AMB debug functionality:
• Reconfigures DDR2 interface to act as a Logic Analyzer Interface (LAI) to observe
activity on FBD high speed links
• Triggers on programmable events in normal operation
1.1.3
DDR SDRAM
DDR2 SDRAM support:
• Supports DDR2 at speeds of 533, 667 MT/s
• Supports 256, 512, 1024, 2048 and 4096 Mb devices in x4 and x8 configurations
• 288 devices/channel (8 DIMMs/channel, 1 and 2 ranks/DIMM)
• 72-bit DDR2 SDRAM unregistered, unbuffered memory interface
1.2
AMB Block Diagram
Figure 1-1 is a conceptual block diagram of the AMB’s data flow and clock domains.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
