14.6.3 Firmware Support Registers................................................................... 221
14.7 DFX Registers (Function 5) ............................................................................... 222
14.7.1 Transparent Mode Registers................................................................... 222
14.7.2 Logic Analyzer Interface (LAI) Registers .................................................. 223
14.7.3 Error Injection Registers........................................................................ 230
14.8 Bring-up and Debug Registers (Function 6)......................................................... 231
14.8.1 SPAD[1:0]: Scratch Pad........................................................................ 231
14.8.2 Southbound FBD Intel® Interconnect BIST Registers................................. 231
14.8.3 Northbound FBD Intel IBIST Registers..................................................... 236
15
A
SPD Bits ................................................................................................................ 243
15.1 Access Mechanisms ......................................................................................... 243
15.1.1 Raw Cards A, B, and C.......................................................................... 243
15.1.2 Raw Cards D, E, H, and J....................................................................... 244
15.1.3 Category Byte 99 ................................................................................. 245
Glossary ................................................................................................................ 247
A.1
Terms and Definitions...................................................................................... 247
Figures
1-1
1-2
2-1
2-2
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
9-1
9-2
Advanced Memory Buffer Block Diagram............................................................... 13
AMB Interfaces ................................................................................................. 14
Delays Through an AMB ..................................................................................... 22
Command to Data Delay Timing.......................................................................... 23
Nominal Turnaround Time Timing Diagram ........................................................... 31
Latency Timing Diagrams ................................................................................... 44
tDVA and tDVB Timing Diagram .......................................................................... 46
tjit and tjitHP Timing Diagram............................................................................. 47
tCVA and tCVB Timing Diagram........................................................................... 47
tECVA and tECVB Timing Diagram ....................................................................... 47
TDQSCK Timing Diagram.................................................................................... 48
DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram .................. 48
Write Preamble Duration Timing Diagram ............................................................. 49
Write Postamble Duration Timing Diagram............................................................ 49
AMB LAI Mode Usage Diagram ............................................................................ 54
AMB LAI Mode Connectivity ................................................................................ 55
LAI Signal Group Timing..................................................................................... 60
LAI Match and Mask Logic .................................................................................. 61
Local Event Mux Block Diagram........................................................................... 62
EVBus Overview................................................................................................ 64
Event Bus Signal Timing..................................................................................... 65
LAI Qualification Signal Block Diagram ................................................................. 66
Block Diagram of AMB in LAI Mode ...................................................................... 67
SMBus Configuration Read (Block Write / Block Read, PEC Enabled)......................... 79
SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ........................ 80
SMBus Configuration Double Word Write (Block Write, PEC Enabled)........................ 80
SMBus Configuration Double Word Write (Write Bytes, PEC Enabled)........................ 81
SMBus Configuration Word Write (Block Write, PEC Disabled).................................. 81
SMBus Configuration Byte Write (Write Bytes, PEC Disabled)................................... 81
AMB Clock Domains........................................................................................... 84
FBD PLL Power Supply Filter ............................................................................... 89
Cold Power-Up Reset ......................................................................................... 96
AMB Fast Reset Sequence .................................................................................. 96
10-1 DRAM Architecture ............................................................................................ 99
Intel® 6400/6402 Advanced Memory Buffer Datasheet
7
INTEL [ INTEL ]
