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    6400 参数 Datasheet PDF下载

    6400图片预览
    型号： 6400
    PDF下载： 下载PDF文件 查看货源
    内容描述： 高级内存缓冲器 [Advanced Memory Buffer]
    分类和应用：
    文件页数/大小： 250 页 / 3863 K
    品牌： INTEL [ INTEL CORPORATION ]
     浏览型号6400的Datasheet PDF文件第1页浏览型号6400的Datasheet PDF文件第2页浏览型号6400的Datasheet PDF文件第3页浏览型号6400的Datasheet PDF文件第4页浏览型号6400的Datasheet PDF文件第6页浏览型号6400的Datasheet PDF文件第7页浏览型号6400的Datasheet PDF文件第8页浏览型号6400的Datasheet PDF文件第9页  
    8
    Clocking
    .................................................................................................................. 83
    8.1
    Intel 6400/6402 Advanced Memory Buffer (AMB) Clock Domains ............................. 83
    8.2
    PLL Clocks ........................................................................................................ 85
    8.3
    Reference Clock ................................................................................................ 85
    8.4
    FBD Lane Frame Clocks...................................................................................... 86
    8.5
    Clock Ratios ..................................................................................................... 86
    8.6
    DDR DRAM Clock Support................................................................................... 86
    8.7
    SMBus ............................................................................................................. 86
    8.8
    Clock Pins ........................................................................................................ 86
    8.9
    Additional Clock Modes....................................................................................... 87
    8.9.1 Transparent Mode Clocking...................................................................... 87
    8.10 PLL Requirements.............................................................................................. 87
    8.10.1 Jitter .................................................................................................... 87
    8.10.2 PLL Bandwidth Requirements ................................................................... 87
    8.10.3 External Reference ................................................................................. 87
    8.10.4 Spread Spectrum Support ....................................................................... 88
    8.10.5 Frequency of Operation ........................................................................... 88
    8.10.6 RESET# ................................................................................................ 88
    8.10.7 Other PLL Characteristics......................................................................... 88
    8.11 Analog Power Supply Pins................................................................................... 89
    Reset
    ....................................................................................................................... 91
    9.1
    Platform Reset Functionality ............................................................................... 91
    9.1.1 Platform RESET# Requirements ............................................................... 91
    9.1.2 RESET# Requirements ............................................................................ 91
    9.1.3 Power-Up and Suspend-to-RAM Considerations .......................................... 92
    9.2
    Reset Types...................................................................................................... 92
    9.3
    Pads Controlling Reset ....................................................................................... 92
    9.3.1 RESET# Pad .......................................................................................... 92
    9.3.2 Primary FBD Link ................................................................................... 93
    9.4
    Details ............................................................................................................. 93
    9.4.1 Cold Power-Up Reset Sequence ................................................................ 93
    9.4.2 S3 Restore Power-Up Reset Sequence ....................................................... 94
    9.4.3 Reset Sequence for a Fast Reset .............................................................. 95
    9.4.4 Fast Reset Handshake............................................................................. 95
    9.4.5 Timing Diagrams .................................................................................... 96
    9.5
    I/O Initialization ................................................................................................ 97
    9.5.1 FBD Channel Initialization........................................................................ 97
    9.5.2 DDR ..................................................................................................... 97
    Transparent Mode
    ................................................................................................... 99
    10.1 Transparent Mode ............................................................................................. 99
    10.1.1 Block Diagram ..................................................................................... 100
    10.1.2 Transparent Mode Signal Definitions ....................................................... 100
    10.1.3 Transparent Mode to FBD Pin Mapping .................................................... 101
    10.2 Transparent Mode Timing ................................................................................. 102
    10.2.1 Clock Frequency and Core Timing ........................................................... 102
    10.2.2 Edge Placement Accuracy ...................................................................... 102
    10.2.3 Transparent Mode Timing ...................................................................... 102
    10.2.4 Error Reporting .................................................................................... 106
    10.2.5 Transparent Mode IO Specifications ........................................................ 107
    10.2.6 IO Implementation Guidelines ................................................................ 108
    10.3 Transparent Mode Control and Status Registers................................................... 109
    DDR
    11.1
    11.2
    11.3
    MemBIST
    ....................................................................................................... 111
    MemBIST Overview ......................................................................................... 111
    MemBIST Feature Summary ............................................................................. 112
    MemBIST Operation......................................................................................... 113
    5
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    Intel® 6400/6402 Advanced Memory Buffer Datasheet

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