4.1.1 Absolute Maximum Ratings ......................................................................37
4.1.2 Operating DC Parameters ........................................................................37
4.1.3 AMB Power Specifications ........................................................................38
FB-DIMM Electrical Timing Specifications...............................................................44
DDR2 DRAM Interface Electrical Specifications.......................................................45
DDR2 Electrical Output Timing Specifications.........................................................46
4.4.1 Description of DQ/DQS Alignment.............................................................46
4.4.2 Description of ADD/CMD/CNTL Outputs......................................................46
4.4.3 Test Load Specification............................................................................46
4.4.4 tDVA and tDVB Parameter Description.......................................................46
4.4.5 tjit and tjitHP Parameter Description..........................................................46
4.4.6 tCVA, tCVB, tECVA and tECVB Parameter Description...................................47
4.4.7 tDQSCK Timing Parameter Description.......................................................47
4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS
4.2
4.3
4.4
(Read Operation)....................................................................................48
4.4.9 Write Preamble Duration..........................................................................49
4.4.10 Write Postamble Duration ........................................................................49
4.4.11 Advance Memory Buffer Component Electrical Timing Summary....................50
4.4.12 Reference DDR2 Interface Package Trace Lengths.......................................51
SMBUS Interface ...............................................................................................51
Miscellaneous I/O (1.5 Volt CMOS Driver) .............................................................51
Thermal Diode and Analog to Digital Converter (ADC).............................................51
4.7.1 Thermal Sensor Effects on the AMB’s
4.5
4.6
4.7
Functional Behavior.................................................................................52
5
Debug and Logic Analyzer Mode...............................................................................53
5.1
Logic Analyzer Interface (LAI) Mode.....................................................................53
5.1.1 LAI Mode Architecture .............................................................................54
5.1.2 LAI Mode Clocking ..................................................................................55
5.1.3 LAI Mode Pins ........................................................................................55
5.1.4 LAI Mode Signal Definitions......................................................................56
5.1.5 LAI to DDR Pin Mapping...........................................................................57
5.1.6 FBD to LAI Signal Mapping.......................................................................58
5.1.7 LAI to DDR Pin Timing.............................................................................59
5.1.8 LAI Features ..........................................................................................60
5.1.9 LAI Block Diagram ..................................................................................67
Normal Mode Debug Features..............................................................................68
5.2.1 Normal Mode Debug Triggers ...................................................................68
5.2.2 Error Injection........................................................................................68
5.2
6
Errors ......................................................................................................................71
6.1
Types of Errors and Responses ............................................................................71
6.1.1 FBD Link Errors ......................................................................................71
6.1.2 DDR Errors ............................................................................................73
6.1.3 Host Protocol Errors ................................................................................73
6.1.4 Other Errors...........................................................................................74
Error Logging....................................................................................................74
6.2.1 Error Logging Procedure ..........................................................................74
Fail Over Mode Support ......................................................................................75
Failback to Pass-Thru .........................................................................................75
6.2
6.3
6.4
7
SMBus Interface ......................................................................................................77
7.1
System Management Access ...............................................................................77
7.1.1 SMBus 2.0 Specification Compatibility........................................................77
7.1.2 Supported SMBus Commands...................................................................77
7.1.3 FBD AMB Register Access Protocols ...........................................................78
7.1.4 SMBus Error Handling..............................................................................81
7.1.5 SMBus Resets ........................................................................................81
4
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
