Contents
1
Introduction............................................................................................................ 11
1.1
Intel® 6400/6402 Advanced Memory Buffer Overview............................................ 11
1.1.1 Transparent Mode for DRAM Test Support.................................................. 12
1.1.2 Debug and Logic Analyzer Interface.......................................................... 12
1.1.3 DDR SDRAM .......................................................................................... 12
AMB Block Diagram ........................................................................................... 12
Interfaces ........................................................................................................ 13
1.3.1 FBD High-Speed Differential Point-to-Point Link (at 1.5 V)
1.2
1.3
Interfaces ............................................................................................ 14
1.3.2 DDR2 Channel ....................................................................................... 14
1.3.3 SMBus Slave Interface ............................................................................ 14
References ....................................................................................................... 15
1.4
2
FBD Channel Interface............................................................................................. 17
2.1
2.2
2.3
Intel 6400/6402 Advanced Memory Buffer (AMB) Support for FBD Operating Modes.. 17
Channel Initialization ......................................................................................... 17
Channel Protocol ............................................................................................... 17
2.3.1 General................................................................................................. 17
2.3.2 Timeouts During TS0 .............................................................................. 17
2.3.3 Recalibrate State Considerations .............................................................. 18
2.3.4 Address Mapping of DDR Commands to DRAMs .......................................... 19
2.3.5 FBD L0s State........................................................................................ 19
Reliability, Availability, and Serviceability ............................................................. 19
2.4.1 Channel Error Detection and Logging ........................................................ 19
Channel Configuration........................................................................................ 19
2.5.1 Re-sync and Resample Modes .................................................................. 19
2.5.2 Other Channel Configuration Modes .......................................................... 20
2.5.3 Lane to Lane Skew on a Channel.............................................................. 20
Repeater Mode.................................................................................................. 21
Channel Latency ............................................................................................... 21
2.7.1 Command to Data Delay Calculation ......................................................... 21
2.4
2.5
2.6
2.7
3
DDR Interface.......................................................................................................... 25
3.1
3.2
3.3
Intel 6400/6402 Advanced Memory Buffer (AMB) DDR Interface Overview ............... 25
Data Mapping ................................................................................................... 25
Command / Address Outputs .............................................................................. 26
3.3.1 CKE Output Control ................................................................................ 27
DQS I/O and DM Outputs ................................................................................... 27
Refresh............................................................................................................ 28
3.5.1 Self-Refresh During Channel Reset ........................................................... 29
3.5.2 Automatic Refresh.................................................................................. 29
Back to Back Turnaround Time............................................................................ 30
S3 State Background Description......................................................................... 31
3.7.1 S3 Recovery Configuration Registers......................................................... 32
DDR Calibration ................................................................................................ 32
3.8.1 DRAM Initialization and (E)MRS FSM......................................................... 32
3.8.2 DQS Failure CSR .................................................................................... 33
3.8.3 Automatic DDR Bus Calibration ................................................................ 34
3.8.4 Receive Enable Calibration....................................................................... 34
3.8.5 DQS Delay Calibration............................................................................. 34
DIMM Organization............................................................................................ 35
3.4
3.5
3.6
3.7
3.8
3.9
4
Electrical, Power, and Thermal ................................................................................ 37
4.1 Electrical DC Parameters .................................................................................... 37
Intel® 6400/6402 Advanced Memory Buffer Datasheet
3
INTEL [ INTEL ]
