DDR MemBIST
11 DDR MemBIST
11.1
MemBIST Overview
The Intel 6400/6402 Advanced Memory Buffer (AMB) supports memory built-in self
test (MemBIST) for memory initialization during system boot up and for testing the
installed memory. During DIMM manufacturing, MemBIST may be used to apply tests
at speed to test the AMB-to-DRAM interface. Table 11-1 below lists the features
provided by MemBIST.
At the system level, MemBIST may be executed on multiple DIMMs simultaneously.
This could be used to speed memory test during system boot.
During DIMM manufacturing, MemBIST offers a fast method to detect FBD assembly-
related defects, interface defects and the majority of memory-core-related defects.
This testing may be done through commands initiated across the FBD channel (in-band
test initiation) or through SMBus or JTAG commands (out-of-band test initiation),
making MemBIST compatible with motherboards, low cost ATE, or standalone
equipment such as continuity testers. To perform in-band testing on a motherboard,
the motherboard must contain an FBD-based memory subsystem.
MemBIST is primarily intended to test the AMB-to-DRAM interface and not the DRAM
core. It is expected that transparent mode will be used to test the core logic in DRAMs
already installed on DIMMs. For this reason, MemBIST includes primarily those
features needed for interface testing. MemBIST does not include all features needed
for DRAM core testing. Traditional system test methods are expected to be used for
operating system or application-based testing of the memory subsystem. This may
include existing memory stress tests, applications or other tests selected by the DIMM
manufacturer.
DDR interface testing requires stress of the AMB DDR I/O circuitry and the DDR I/O-to-
core path in the DRAM. The test needs to be able to detect static faults (such as stuck
signals) as well as dynamic faults (for example, slow timing paths) in the logic.
Testing this logic requires:
• Delivering patterns at full speed (667 MT/S).
• Incrementing and decrementing addresses. The address decoders are best tested
with marching or other non-linear patterns.
• Alternating data patterns (single rotating bits, checkerboards) to detect slow nodes
or capacitive coupling in the data path.
• Using standard interface timing (nominal clock cycle time, setup, hold, pre and
post-amble).
• Verifying ODT operation at speed
To accomplish the required testing, MemBIST has a number of modes of operation and
data formats which can be chosen to meet the specific need. In addition, MemBIST
supports a variety of DRAM timings and densities.
A fundamental feature of the MemBIST architecture is that, unlike transparent mode,
which simply replicates 8 bits of data across the DQ bus, MemBIST can control
individual bits in the 72 bit DQ bus. In addition, MemBIST can apply test patterns at a
rate as high as the DRAM address rate. To accomplish this, the MemBIST architecture
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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INTEL [ INTEL ]
