Transparent Mode
10.2.4.2
Direct Access - Testing of Individual DRAMs
In certain cases it is desirable to test one or two DRAMs. Transparent mode allows
direct access to a single x8 or two x4 DRAMs. In this mode 8 DDR DQ pins are
demultiplexed onto 16 SDR status pins, providing16 bit input data path (on TDQ) and a
16 bit output data path on the status pins.
The transparent mode configuration register has one bit (ENDOUT) to enable this
mode. On reads, the DRAMRD bits will select the bytes of DRAM data to be presented
on the status pins. On writes the DRAMWR bits select a DRAM to receive data from the
TDQ bus. A separate register holds 8 bits of default data to be applied to non-selected
DRAMs in the early/even cycles and another 8 bits for late/odd cycles. The mapping of
these bits to DQ selection is illustrated in the following table.
Table 10-4. Selection of 8 bit Data Paths When ENDOUT is Set
Early Data
DQ Byte
Late Data
DQ Byte
DRAM RD/WR
DQ
0xF (DRAM WR only)
All Bytes
8
7
6
5
4
3
2
1
0
71:64
63:56
55:48
47:40
39:32
31:24
23:16
15:8
8
7
6
5
4
3
2
1
0
17
16
15
14
13
12
11
10
9
7:0
DRAMWR is the byte of data bus selected to receive transparent write data, and byte of
data bus to be compared against transparent read data. DRAMWR allows a setting of
0xF (all ones) which sends the TDQ input data to all DQ bytes. DRAMRD is the byte of
data bus selected to be output on transparent data/status pins when ENDOUT bit is set.
10.2.5
Transparent Mode IO Specifications
Listed below are the specifcations for transparent mode input and output pins.
Table 10-5. Transparent Mode FB-DIMM Interface Signaling Specifications (Sheet 1 of 2)
Minimum
Maximum
500
Units
I/O voltage swing
0
2
mV
Input slew rate
V/ns
ps
Input to refclk (rising or falling edges) setup time
3000
1000
-1000
200
Input to refclk (rising or falling edges) hold time
ps
Status output valid to refclk time
+1000
300
ps
Vref
mV
mV
mV
mV
Vil (DC)
Vil (AC)
Vih (DC)
-300
-300
300
200
150
900
Intel® 6400/6402 Advanced Memory Buffer Datasheet
107
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