DDR MemBIST
provides two 72 bit words, or 144 bits of test data for each DRAM clock cycle. The data
is supplied to the DRAMs on “early” and “late” phases of the DDR clock cycle. Early data
is provided on the rising edge of CK. Late data is provided one half cycle later on the
falling edge of CK. DRAM compare data is treated in a similar manner with appropriate
clock alignment.
11.2
MemBIST Feature Summary
Table 11-1 lists the features of MemBIST in summary form. Each feature is explained
in subsequent sections. The registers used to control these features are detailed in the
MemBIST register section.
Table 11-1. MemBIST Feature Summary (Sheet 1 of 2)
Feature
Feature Description
Memory Address Control
Address pattern in tests
User defined start and end physical address
Fast X, Fast Y, Fast XY, XZY address modes
Choice of incrementing or decrementing addresses
Dynamic address inversion (DAI) inverts alternate addresses
Up to 16
X (row) address bits
Y (column) address bits
Z (bank) address bits
Up to 13 (limited by MTR:numcol to A[13:11,9:0])
Up to 3
Data Patterns
Static data patterns
fixed nibble data patterns (0, 3, 5, 6, 9, A, C, F)
144-bit user-defined data pattern
288-bit user-defined data pattern
Dynamic data patterns
32-bit user-defined circular shifted data pattern
Random data pattern derived from user-specified 32-bit seed using
an LFSR (CRC32)
Data pattern inversion
Any data pattern can be inverted before being applied
Programmable DRAM Timing Control
DDR2 DRAM timing
Burst Length
Set in AMB registers
4 or 8
Refresh control
DDR2 refresh intervals programmable in AMB registers
BIST Engine Control
Fundamental commands
Write, read, read with data compare, write + read with data compare
all registers and settings accessible using FBD, JTAG, or SMBus
x4 or x8
Access method
DRAM data width
DRAM initialization and mode settings Set by AMB registers
Execution speed
Execution control
A programmable number of deselect commands may be inserted
after DRAM accesses to slow down the speed of execution
Halt on error or run to completion of test
Test abort during the test
112
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
