Transparent Mode
200 ps. Flop setup variation should also be less than 200 pS. After removing 400 ps for
clock uncertainties leaves 3.9 ns margin. While this is plenty of margin, some amount
of trace matching should be done on the tester interface to minimize skew.
10.2.6.4
Outgoing Control Signals
Only the TX+ pin should connect to the tester. The data on TX- can be discarded (it will
toggle at the same rate as TX+).
Terminating TX+ on the tester should be a given, as every tester offers this capability.
Terminating TX- could be done on the tester, by having a TIU (tester board) with a
route and a tester connection allocated for it. It may be cheaper to just have a 50 ohm
resistor tied to ground on the TIU itself, from the TX- pins.
To avoid the crossing clock domains from core clock to FBD fast clocks, the transparent
mode data flows directly through the Analog Front-end Unit of the TX.
10.2.6.5
Usage Models
Host Side Usage
10.2.6.5.1
TX: The transmitters are set the same as in normal operation (bias on, enable
termination, and so forth.).
RX: RX+ and RX- signals will be independent. Incoming data will free-flow through the
I/O (no flops). The routing distance from transparent_rxout pins should be the same
for all capture flops. All these flops should be clocked by the dedicated HVM clock.
10.2.6.5.2
Tester Side Usage
The tester interface should have trace-matched data signals, to avoid skews > 1 ns.
The tester should have 50 ohm terminations to ground for all TX pins in use (on-tester
termination can be used where applicable). The tester should enable 50 ohm
terminations to ground for all the signals sent to RX pins. This will guarantee
reasonable signal integrity.
10.3
Transparent Mode Control and Status Registers
In transparent mode, CSRs will be accessed and programmed through SMBus. See
Section 14.3.5, ‚ “Hardware Configuration Registers,” for register descriptions.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
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