Electrical Characteristics
Page 7
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 2 of 2)
Symbol
Description
Devices
Minimum
(4)
0.82
V
CCR_GXBR
Typical
0.85
0.90
1.0
1.05
1.05
0.85
0.90
1.0
1.05
0.85
0.90
1.0
1.05
1.05
1.05
1.5
1.5
Maximum
(4)
0.88
0.93
1.03
1.07
1.08
0.88
0.93
1.03
1.07
0.88
0.93
1.03
1.07
1.08
1.08
1.575
1.575
Unit
Receiver analog power supply (right side)
GX, GS, GT
0.87
0.97
1.03
V
V
CCR_GTBR
Receiver analog power supply for GT
channels (right side)
GT
1.02
0.82
V
V
CCT_GXBL
Transmitter analog power supply (left side)
GX, GS, GT
0.87
0.97
1.03
0.82
0.87
0.97
1.03
V
V
CCT_GXBR
Transmitter analog power supply (right side)
GX, GS, GT
V
V
CCT_GTBR
V
CCL_GTBR
V
CCH_GXBL
V
CCH_GXBR
Transmitter analog power supply for GT
channels (right side)
Transmitter clock network power supply
Transmitter output buffer power supply (left
side)
Transmitter output buffer power supply
(right side)
GT
GT
GX, GS, GT
GX, GS, GT
1.02
1.02
1.425
1.425
V
V
V
V
Notes to
Table 7:
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
you can connect this supply to either 3.0 V or 2.5 V.
(2) Refer to
to select the correct power supply level for your design.
(3) When using ATX PLLs, the supply must be 3.0 V.
(4) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to
the PDN tool for the additional budget for the dynamic tolerance requirements.
December 2015
Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL CORPORATION ]
