Electrical Characteristics
Page 11
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 2 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C3, I3,
I3YY
C1
C2,I2
C4, I4
Internal series termination
without calibration (50-
setting)
50- RS
VCCIO = 1.8 and 1.5 V
VCCIO = 1.2 V
30
30
40
40
%
Internal series termination
without calibration (50-
setting)
50- RS
35
25
35
25
50
25
50
25
%
%
Internal differential
termination (100- setting)
100- RD
VCCIO = 2.5 V
Calibration accuracy for the calibrated series and parallel OCTs are applicable at the
moment of calibration. When voltage and temperature conditions change after
calibration, the tolerance may change.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 13 lists the OCT variation with temperature and voltage after power-up
calibration. Use Table 13 to determine the OCT variation after power-up calibration
and Equation 1 to determine the OCT variation without recalibration.
(4), (5), (6)
Equation 1. OCT Variation Without Recalibration for Stratix V Devices (1), (2), (3),
dR
dT
dR
dV
------
-------
V
ROCT = R
1 +
T
SCAL
Notes to Equation 1:
(1) The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO
(2) RSCAL is the OCT resistance value at power-up.
.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 13 lists the on-chip termination variation after power-up calibration.
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 1 of 2) (1)
Symbol
Description
VCCIO (V)
3.0
Typical
0.0297
0.0344
0.0499
0.0744
0.1241
Unit
2.5
OCT variation with voltage without
recalibration
dR/dV
1.8
%/mV
1.5
1.2
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
