Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–5
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–4 shows the user I/O BSC for MAX V devices.
Figure 8–4. User I/O BSC with IEEE Std. 1149.1 BST Circuitry for MAX V Devices
SDO
PIN_IN
INJ
0
1
D
Input
Q
PIN_OE
OEJ
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE
OE
From or To Device
I/O Cell Circuitry
And/Or Logic Core
OUTJ
PIN_OUT
0
1
0
1
D
Q
Pin
Output
Output
Output
Buffer
SHIFT
CLOCK
UPDATE
HIGHZ MODE
Global Signals
Capture
Registers
Update
Registers
SDI
Table 8–2 lists the capture and update register capabilities of all BSC within MAX V
devices.
Table 8–2. BSC Description for MAX V Devices (Note 1)
Captures
Drives
Output
Capture
Register
Output
Update
Register
Pin Type
Notes
OE Capture
Register
InputCapture
Register
OE Update Input Update
Register
Register
Includes
user clocks
User I/O
OUTJ
OEJ
PIN_IN
PIN_OUT
PIN_OE
—
Note to Table 8–2:
(1) TDI, TDO, TMS, and TCKpins and all VCCand GNDpin types do not have BSCs.
JTAG Pins and Power Pins
MAX V devices do not have BSCs for dedicated JTAG pins (TDI, TDO, TMS, and TCK)
and power pins (VCCINT VCCIO GNDINT, and GNDIO).
,
,
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
