Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–9
IEEE Std. 1149.1 BST Operation Control
Figure 8–8 shows the capture, shift, and update phases of SAMPLE/PRELOADmode.
Figure 8–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
SDO
PIN_IN
INJ
0
1
D
Input
Q
PIN_OE
OEJ
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE
OE
OUTJ
PIN_OUT
0
1
0
1
D
Q
Pin
Output
Output
Output
Buffer
SHIFT
CLOCK
UPDATE
HIGHZ MODE
Global Signals
Capture
Registers
Update
Registers
SDI
(Capture Phase)
SDO
PIN_IN
INJ
0
1
D
Input
Q
PIN_OE
OEJ
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE
OE
OUTJ
PIN_OUT
0
1
0
1
D
Q
Pin
Output
Output
Output
Buffer
SHIFT
CLOCK
UPDATE
HIGHZ MODE
Global Signals
Capture
Registers
Update
Registers
SDI
(Shift and Update Phase)
SAMPLE/PRELOADinstruction code shifts in through the TDIpin. The TAP controller
advances to the CAPTURE DRstate and then to the SHIFT DRstate, where it remains if
TMSis held low. The data shifted out of the TDOpin consists of the data that was
_
_
present in the capture registers after the capture phase. New test data shifted into the
TDIpin appears at the TDOpin after being clocked through the entire boundary-scan
register.
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
