Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–3
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–2 shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 8–2. IEEE Std. 1149.1 Circuitry
Instruction Register
TDI
TDO
UPDATEIR
CLOCKIR
SHIFTIR
Instruction Decode
TAP
TMS
TCK
Controller
Data Registers
Bypass Register
UPDATEDR
CLOCKDR
SHIFTDR
Boundary-Scan Register (1)
a
Device ID Register
ISP Registers
Note to Figure 8–2:
(1) For the boundary-scan register length in MAX V devices, refer to the JTAG and In-System Programmability in MAX V Devices chapter.
The TAP controller controls the IEEE Std. 1149.1 boundary-scan testing, as described
in “IEEE Std. 1149.1 BST Operation Control” on page 8–6. The TMSand TCKpins
operate the TAP controller and the TDIand TDOpins provide the serial path for the
data registers. The TDIpin also provides data to the instruction register, which then
generates the control logic for the data registers.
IEEE Std. 1149.1 Boundary-Scan Register
The boundary-scan register is a large serial shift register that uses the TDIpin as an
input and the TDOpin as an output. The boundary-scan register consists of 3-bit
peripheral elements that are associated with the I/O pins of the MAX V devices. You
can use the boundary-scan register to test the external pin connections or to capture
internal data.
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
