8–8
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Operation Control
The TDOpin is tri-stated in all states except the SHIFT_IRand SHIFT_DRstates. The TDO
pin is activated at the first falling edge of TCKafter entering either of the shift states
and is tri-stated at the first falling edge of TCKafter leaving either of the shift states.
When the SHIFT
the instruction register is shifted out on the falling edge of TCK
out the contents of the instruction register as long as the SHIFT
TAP controller remains in the SHIFT IRstate as long as TMSremains low.
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IRstate is activated, TDOis no longer tri-stated, and the initial state of
TDOcontinues to shift
IRstate is active. The
.
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During the SHIFT IRstate, an instruction code is entered by shifting data on the TDI
pin on the rising edge of TCK. You must clock the last bit of the OPCODEat the same time
that the next state, EXIT1 IR, is activated; EXIT1 IRis entered by clocking a logic high
on TMS. After in the EXIT1 IRstate, TDO becomes tri-stated again. TDOis always
tri-stated except in the SHIFT IRand SHIFT DRstates. After an instruction code is
entered correctly, the TAP controller advances to perform the serial shifting of test
data in one of three modes (SAMPLE EXTEST, or BYPASS).
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PRELOAD,
For MAX V devices, there are weak pull-up resistors for TDIand TMS, and pull-down
resistors for TCK. However, in a JTAG chain, there might be some devices that do not
have internal pull-up or pull-down resistors. In this case, Altera recommends pulling
the TMSpin high (through an external 10-k resistor), and pulling TCKlow (through an
external 1-k resistor) during BST or in-system programmability (ISP) to prevent the
TAP controller from going into an unintended state. Pulling-up the TDIsignal
externally for the MAX V device is optional.
f For more information about the pull-up and pull-down resistors, refer to
AN 100: In-System Programmability Guidelines.
SAMPLE/PRELOAD Instruction Mode
SAMPLE/PRELOADinstruction mode allows you to take a snapshot of device data
without interrupting normal device operation. However, SAMPLE/PRELOADinstruction
mode is most often used to preload the test data into the update registers before
loading the EXTESTinstruction.
During the capture phase, multiplexers preceding the capture registers select the
active device data signals and clocked data into the capture registers. The
multiplexers at the outputs of the update registers also select active device data to
prevent functional interruptions to the device.
During the shift phase, the boundary-scan shift register is formed by clocking data
through capture registers around the device periphery and then out of the TDOpin.
New test data can simultaneously be shifted into TDIand replace the contents of the
capture registers. During the update phase, data in the capture registers is transferred
to the update registers.You can then use this data in EXTESTinstruction mode. For
more information, refer to “EXTEST Instruction Mode” on page 8–10.
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
