8–2
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Architecture
■
■
■
“Disabling IEEE Std. 1149.1 BST Circuitry” on page 8–15
“Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing” on page 8–15
“Boundary-Scan Description Language Support” on page 8–15
In addition to BST, you can use the IEEE Std. 1149.1 controller for in-system
programming for MAX V devices. MAX V devices support IEEE 1532 programming,
which uses the IEEE Std. 1149.1 test access port (TAP) interface. However, this chapter
only describes the BST feature of the IEEE Std. 1149.1 circuitry.
IEEE Std. 1149.1 BST Architecture
A MAX V device operating in IEEE Std. 1149.1 BST mode uses four required pins, TDI
,
TDO TMS, and TCK
,
.
Table 8–1 lists the functions of each of these pins. MAX V devices do not have a TRST
pin.
Table 8–1. IEEE Std. 1149.1 Pin Descriptions
Pin
Description
Function
Serial input pin for instructions as well as test and
programming data. Data is shifted in on the rising edge of TCK
TDI (1)
Test data input
.
Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge of
TCK. The pin is tri-stated if data is not being shifted out of the
device.
TDO
Test data output
Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
TMS (1)
TCK (2)
Test mode select
Test clock input
within the state machine occur at the rising edge of TCK
Therefore, you must set up the TMSbefore the rising edge of
TMSis evaluated on the rising edge of TCK
.
TCK
.
.
The clock input to the BST circuitry. Some operations occur at
the rising edge, while others occur at the falling edge.
Notes to Table 8–1:
(1) The TDIand TMSpins have internal weak pull-up resistors
(2) The TCKpin has an internal weak pull-down resistor
The IEEE Std. 1149.1 BST circuitry requires the following registers:
■
■
■
The instruction register determines which action to perform and which data
register to access.
The bypass register (which is a 1-bit long data register) provides a
minimum-length serial path between the TDIand TDOpins.
The boundary-scan register that is a shift register composed of all the BSCs of the
device.
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
