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5CSEMA5U23I7N 参数 Datasheet PDF下载

5CSEMA5U23I7N图片预览
型号: 5CSEMA5U23I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA672, ROHS COMPLIANT, UBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 66 页 / 1360 K
品牌: INTEL [ INTEL ]
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Glossary  
Page 59  
Glossary  
Table 63 lists the glossary for this datasheet.  
Table 63. Glossary Table (Part 1 of 4)  
Letter  
Subject  
Definitions  
A
B
C
Receiver Input Waveforms  
Single-Ended Waveform  
Positive Channel (p) = V  
IH  
V
ID  
Negative Channel (n) = V  
Ground  
IL  
V
CM  
Differential Waveform  
V
ID  
p n = 0 V  
V
ID  
Differential I/O  
Standards  
D
Transmitter Output Waveforms  
Single-Ended Waveform  
Positive Channel (p) = V  
OH  
V
OD  
Negative Channel (n) = V  
Ground  
OL  
V
CM  
Differential Waveform  
V
OD  
p n = 0 V  
V
OD  
E
F
fHSCLK  
Left/right PLL input clock frequency.  
High-speed I/O block—Maximum/minimum LVDS data transfer rate  
(fHSDR = 1/TUI).  
fHSDR  
G
H
I
July 2014 Altera Corporation  
Cyclone V Device Datasheet  
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