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Switching Characteristics
Table 23. Transceiver Compliance Specification for All Supported Protocol for Cyclone V
Devices (Part 2 of 2)
Protocol
Sub-protocol
Data Rate (Mbps)
HiGig+
HIGIG 3750
3,750
Notes to Table 23:
(1) For PCIe Gen2 sub-protocol, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V
to 1.2 V for Cyclone V GT FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter
specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and
ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(2) For CPRI E48LVII and E60LVII, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V
to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and
6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in
Cyclone V Devices chapter.
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
