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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-81  
Initialization  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
s
tCH  
tCL  
DCLKhigh time  
DCLKlow time  
DCLKperiod  
0.45 × 1/fMAX  
0.45 × 1/fMAX  
s
tCLK  
1/fMAX  
s
fMAX  
DCLKfrequency  
CONF_DONEhigh to user mode(105)  
175  
125  
437  
MHz  
µs  
tCD2UM  
tCD2CU  
tCD2UMC  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLKperiod  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (Tinit × CLKUSR  
period)  
Tinit  
Number of clock cycles required for device initialization  
17,408  
Cycles  
Related Information  
PS Configuration Timing  
Provides the PS configuration timing waveform.  
Initialization  
Table 1-71: Initialization Clock Source Option and the Maximum Frequency for Arria V Devices  
Initialization Clock Source  
Configuration Scheme  
AS, PS, and FPP  
PS and FPP  
Maximum Frequency (MHz)  
Minimum Number of Clock Cycles  
Internal Oscillator  
12.5  
125  
100  
125  
CLKUSR(106)  
Tinit  
AS  
DCLK  
PS and FPP  
(105)  
(106)  
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.  
To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime  
software from the General panel of the Device and Pin Options dialog box.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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