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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-85  
Programmable IOE Delay  
The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete  
place-and-route.  
Related Information  
Arria V I/O Timing Spreadsheet  
Provides the Arria V Excel-based I/O timing spreadsheet.  
Programmable IOE Delay  
Table 1-76: I/O element (IOE) Programmable Delay for Arria V Devices  
Fast Model  
Slow Model  
–C6  
Parameter(111  
Available  
Settings  
Minimum  
Offset(112)  
Unit  
)
Industrial  
Commercial  
0.517  
–C4  
–C5  
–I3  
–I5  
D1  
D3  
D4  
D5  
32  
8
0
0
0
0
0.508  
1.763  
0.508  
0.508  
0.870  
2.999  
0.869  
0.870  
1.063  
3.496  
1.063  
1.063  
1.063  
0.872  
1.057  
ns  
ns  
ns  
ns  
1.795  
3.571  
3.031  
1.063  
0.872  
3.643  
1.057  
1.057  
32  
32  
0.518  
1.063  
0.517  
1.063  
(111)  
You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.  
Minimum offset does not include the intrinsic delay.  
(112)  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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