AV-51002
2015.12.16
1-80
DCLK Frequency Specification in the AS Configuration Scheme
DCLK Frequency Specification in the AS Configuration Scheme
Table 1-69: DCLK Frequency Specification in the AS Configuration Scheme
This table lists the internal clock frequency specification for the AS configuration scheme. The DCLKfrequency specification applies when you use the
internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
Parameter
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLKfrequency in AS configuration scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Table 1-70: PS Timing Parameters for Arria V Devices
Symbol
Parameter
Minimum
Maximum
600
Unit
ns
ns
µs
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
—
—
600
2
—
nSTATUSlow pulse width
268
—
1506(102)
1506(103)
—
µs
nCONFIGhigh to nSTATUShigh
µs
(104)
tCF2CK
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
1506
2
µs
(104)
tST2CK
tDSU
tDH
—
µs
5.5
0
—
ns
ns
—
(102)
(103)
(104)
You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
Arria V GX, GT, SX, and ST Device Datasheet
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