AV-51002
2015.12.16
1-77
FPP Configuration Timing when DCLK-to-DATA[] >1
Symbol
Parameter
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
Minimum
Maximum
Unit
µs
ns
ns
s
(95)
tST2CK
2
—
—
tDSU
5.5
tDH
0
—
tCH
0.45 × 1/fMAX
—
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
s
fMAX
tCD2UM
tCD2CU
tCD2UMC
DCLKfrequency (FPP ×8/ ×16)
CONF_DONEhigh to user mode(96)
CONF_DONEhigh to CLKUSRenabled
CONF_DONEhigh to user mode with CLKUSRoption on
—
175
125
437
—
MHz
µs
—
—
4× maximum DCLKperiod
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 1-67: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
Minimum
Maximum
600
Unit
ns
tCF2CD
tCF2ST0
tCFG
nCONFIGlow to CONF_DONElow
—
—
2
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
600
ns
—
µs
(96)
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GX, GT, SX, and ST Device Datasheet
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