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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-79  
AS Configuration Timing  
AS Configuration Timing  
Table 1-68: AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices  
The minimum and maximum numbers apply to both the internal oscillator and CLKUSRwhen either one is used as the clock source for device configura‐  
tion.  
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing  
Parameters for Arria V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUSlow.  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
ns  
tCO  
tSU  
DCLKfalling edge to the AS_DATA0/ASDOoutput  
Data setup time before the falling edge on DCLK  
Data hold time after the falling edge on DCLK  
CONF_DONEhigh to user mode  
2
1.5  
ns  
tDH  
0
175  
ns  
tCD2UM  
tCD2CU  
437  
µs  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLKperiod  
tCD2UMC  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (Tinit × CLKUSR  
period)  
Tinit  
Number of clock cycles required for device initialization  
17,408  
Cycles  
Related Information  
PS Configuration Timing on page 1-80  
AS Configuration Timing  
Provides the AS configuration timing waveform.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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